Semiconductor packages and methods for forming the same

ABSTRACT

Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and exposed on edge surfaces of the integrated circuit die. The edge interconnect features are configured to connect with other integrated circuit dies without going through an interposer. The semiconductor device may include two or more integrated circuit dies with edge interconnect features and connected through one or more inter-chip connectors formed between the two or more integrated circuit dies. In some embodiments, the inter-chip connectors may be formed by a selective bumping process during packaging.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 17/382,916, filed Jul. 22, 2021, which claims priority to aU.S. Provisional Patent Application Ser. No. 63/156,212, filed Mar. 3,2021. Each of the aforementioned patent application is incorporated byreference in its entirety.

BACKGROUND

The semiconductor industry continues to improve the integration densityof various electronic components (e.g., transistors, diodes, resistors,capacitors, etc.) by continual reductions in minimum feature size, whichallow more components, hence more functions, to be integrated into agiven area, forming integrated circuit dies. Each integrated circuit diemay include many input/output pads to communicate with other componentsto be packaged with the integrated circuit die. Interposers are commonlyused to provide input/output among two or more integrated circuit diesin a semiconductor package. However, integration density increases,connecting integrated circuit dies through interposers alone may becomechallenging.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A-1L schematically demonstrate an integrated circuit die havingedge interconnect features according to embodiments of the presentdisclosure.

FIGS. 2, 3A-3D, 4A-4D, 5A-5B, 6, and 7 schematically demonstrate variousstages of forming a semiconductor package according to embodiments ofthe present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “over,” “top,” “upper” and the like, may be used herein forease of description to describe one element or feature's relationship toanother element(s) or feature(s) as illustrated in the figures. Thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. The apparatus may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein may likewise be interpretedaccordingly.

Embodiments discussed herein may be discussed in a specific context,namely a package structure (e.g., a package on package (PoP) structure)including dies bonded together with a hybrid bonding technique. The diescan be bonded together face-to-face (F2F) or face-to-back (F2B). Forexample, in a F2F bonding configuration the active surfaces (faces) ofthe dies are bonded together, whereas in a F2B bonding configuration, anactive surface of one die is bonded to a back surface of another die. Inaddition, the hybrid bonding between the dies includes adielectric-to-dielectric bonding and a metal bonding. For example, byincluding a solder bonding (instead of, for example, copper to copperbonding), the bonding temperature of the hybrid bonding can be loweredsignificantly.

Further, the teachings of this disclosure are applicable to any packagestructure including one or more semiconductor dies. Other embodimentscontemplate other applications, such as different package types ordifferent configurations that would be readily apparent to a person ofordinary skill in the art upon reading this disclosure. It should benoted that embodiments discussed herein may not necessarily illustrateevery component or feature that may be present in a structure. Forexample, multiples of a component may be omitted from a figure, such aswhen discussion of one of the components may be sufficient to conveyaspects of the embodiment. Further, method embodiments discussed hereinmay be discussed as being performed in a particular order; however,other method embodiments may be performed in any logical order.

Embodiments of the present disclosure provide an integrated circuit diehaving edge interconnect features. The edge interconnect features may beconductive lines extending through sealing rings and exposed on edgesurfaces of the integrated circuit die. The edge interconnect featuresare configured to connect with another integrated circuit die withoutgoing through an interposer. The semiconductor device may include two ormore integrated circuit dies with edge interconnect features andconnected through one or more edge bumping features formed between thetwo or more integrated circuit dies. In some embodiments, the edgebumping features may be formed by a selective metal bumping processduring packaging.

FIGS. 1A-1L schematically demonstrate an integrated circuit die havingedge interconnect features according to embodiments of the presentdisclosure. FIG. 1A is a schematic plan view of a substrate including anarray of integrated circuit dies according to the present disclosure.FIG. 1B is a schematic plan view of one integrated circuit die 100 (100a, 100 b) according to the present disclosure. FIG. 1C is an enlargedpartial sectional view of the integrated circuit die 100 along the line1C-1C in FIG. 1B. FIG. 1D is an enlarged partial sectional view of theintegrated circuit die 100 along the line 1D-1D in FIG. 1C.

As shown in FIG. 1A, an array of integrated circuit dies (or chiplets)100 are formed on a substrate 10. The array of integrated circuit dies100 are separated from each other by two sets of intersecting scribelines 12. One set of scribe lines 12 extend along the x-direction and asecond set of scribe lines 12 extend along the y-direction. The array ofintegrated circuit dies 100 are formed in and/or on the substrate 10within an array of areas defined by the scribe lines 12. Afterfabrication, the integrated circuit dies 100, may be tested and cut outalong the scribe lines 12 to individual integrated circuit dies 100 forsubsequent processing, such as packaging.

As shown in FIG. 1A, each of the integrated circuit die 100 may includea circuit region 104 surrounded by a seal region 106. According toembodiments of the present disclosure, the integrated circuit die 100includes one or more edge interconnect features 108 extending from thecircuit region 104 through the seal region 106 into the scribe line 12.In some embodiments, the edge interconnect features 108 may beconductive lines intersecting with the scribe lines 12 surrounding theintegrated circuit die 100. After the integrated circuit die 100 is cutout along the scribe lines 12, the edge interconnect features 108 areexposed on cutting surfaces 102 of the integrated circuit die 100. Theedge interconnect features 108 may be conductive lines configured toconnect with external contacts formed on the cutting surfaces 102 toprovide signal and/or power supplies. In some embodiments, the edgeinterconnect features 108 may be symmetrically arranged across allscribe lines 12 around the integrated circuit die 100.

The substrate 10 may be a semiconductor substrate, for example, bulksilicon, doped or undoped, or an active layer of asemiconductor-on-insulator (SOI) substrate. The semiconductor substratemay include other semiconductor material, such as germanium; a compoundsemiconductor including silicon carbide, gallium arsenic, galliumphosphide, indium phosphide, indium arsenide, and/or indium antimonide;an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs,GaInP, and/or GaInAsP; or combinations thereof. Other substrates, suchas a multi-layered or gradient substrate may also be used.

The array of integrated circuit dies 100 may be formed in and/or on thesubstrate 10 by performing various semiconductor fabrication processes,including, but not limited to, front-end-of-line (FEOL) processing, andback-end-of-line (BEOL) processing. The various semiconductorfabrication processes are performed to form a device layer 120 (FIGS. 1Cand 1D) and an interconnect structure 122 (FIGS. 1C and 1D) in theintegrated circuit dies 100.

In some embodiments, the array of integrated circuit dies 100 havesubstantially identical circuit designs. In other embodiments, the arrayof integrated circuit dies 100 may include two or more different circuitdesigns formed on the same substrate 10. The integrated circuit dies 100may be designed to perform any suitable function. For example, theintegrated circuit die 100 may be a logic die (e.g., central processingunit, a SoC, ASIC, FPGA, microcontroller, etc.), a memory die (e.g., aDRAM die, a Wide I/O die, a M-RAM die, a R-RAM die, a NAND die, an SRAMdie, etc.), a memory cube (e.g., HBM, HMC, etc.), a high data ratetransceiver die, an I/O interface die, an integrated passive device die(e.g., an IPD die), a power management die (e.g., a PMIC die), an RFdie, a sensor die, an MEMS die, signal processing dies (e.g., a DSPdie), a front-end die (e.g., an AFE dies), a monolithic 3D heterogeneouschiplet stacking die, the like, or a combination thereof.

FIG. 1B is a schematic plan view of two neighboring integrated circuitdies 100 a, 100 b according to the present disclosure formed on thesubstrate 10. In FIG. 1B, components formed in various layers along thez-axis are superimposed on one another to show their relative positionsin plan view. Positions of the components along the z-axis are showncorresponding cross-sectional views, such as the views in FIGS. 1C and1D. FIG. 1B illustrates relative positions of the circuit region 104,the seal region 106, and the edge interconnect features 108 within theintegrated circuit dies 100 according to some embodiments. As shown inFIG. 1B, each integrated circuit die 100 is defined in a square area bythe scribe lines 12. In some embodiments, the integrated circuit dies100 may have a plan view area in a range between about 10 mm² and about1000 mm² depending on the circuit design and/or function of theintegrated circuit die 100. FIG. 1B illustrates integrated circuit dieswith a square shape in the plan view. However, the integrated circuitdies may have other shapes in the plan view. For example, rectangular,hexagonal, octagonal shapes may be used to achieve design purposes.Depending on the design, the scribe lines 12 may have a width 12 w in arange between about 1 μm to about 200 μm. A scribe line width 12 w lowerthan 1 μm may not be wide enough to tolerant system errors duringseparation of the integrated circuit dies 100. A scribe line width 12 wgreater than 200 μm would increase cost of production without additionalbenefit.

Within the die area of each integrated circuit die 100, the circuitregion 104 is surrounded by the seal region 106 around an outerperimeter of the circuit region 104. One or more sealing rings 110, 112are concentrically formed in the seal region 106. The seal rings 110,112 provide protection to circuit structures in the circuit region 104against undesired elements from the exterior environment, such as watervapor, during and after separation of the integrated circuit dies 100.

Even though two sealing rings 110, 112 are shown in the integratedcircuit die 100, less or more sealing rings may be included in the sealregion 106. After being cut along the scribe lines 12, the portion ofthe scribe line 12 may remain on sides of the integrated circuit die100, and the seal region 106 is surrounded by materials of the scribelines 12 and not exposed on the cutting surfaces 102.

The edge interconnect features 108 are two or more conductive linesextending from the circuit region 104 through the seal region tointersect with the scribe lines 12. In some embodiments, the edgeinterconnect features 108 may intersect with the corresponding scribeline 12 at a substantially perpendicular manner. In other embodiments,the edge interconnect features 108 may intersect with the correspondingscribe line 12 at a slanted angle. For example, the edge interconnectfeatures 108 may intersect the y-z plan at a slanted angle, such as anangle in a range between about 45 degree to about 90 degree. In someembodiments, the edge interconnect features 108 may be distributed alongone or more of sides 106 s of the seal region 106. In some embodiments,the edge interconnect features 108 are a plurality of conductive linesdistributed along one or more of the sides 106 s. In some embodiments,the plurality of conductive lines may be evenly distributed along one ormore sides 106 s of the seal region 106.

In some embodiments, as shown in FIG. 1B, the edge interconnect features108 may be symmetrically arranged along all sides 106 s of the sealregion 106. For example, an equal number of the edge interconnectfeatures 108 are distributed alone every sides 106 s of the seal region106 at a substantially equal pitch. The symmetrical distribution allowcorresponding edge interconnect features 108 in neighboring integratedcircuit dies 100 to form continuous conductive lines. As shown in FIG.1B, edge interconnect features 108 a of the integrated circuit die 100 aare in contact with corresponding edge interconnect features 108 b ofthe integrated circuit die 100 a to form a plurality of continuousconductive lines across the shared scribe line 12. Similarly, the edgeinterconnect features 108 a along other sides 106 s of the seal region106 may form continuous line features with corresponding edgeinterconnect features 108 in the neighboring integrated circuit die 100along the other sides 106 s.

In some embodiments, the edge interconnect features 108 a of theintegrated circuit die 100 a and the corresponding edge interconnectfeatures 108 b of the integrated circuit die 100 b are fabricated asmonolithic conductive lines. The monolithic conductive line arrangementmay enable direct communication between devices in the neighboringintegrated circuit dies, and thus, allowing the neighboring integratedcircuit dies to be packaged together without cutting from the scribelines. The monolithic conductive line arrangement also provides highertolerance to the cutting operation and ensures that the edgeinterconnect features 108 are exposed on the cutting surface 102.

In other embodiments, the edge interconnect features 108 a of theintegrated circuit die 100 a and the corresponding edge interconnectfeatures 108 b of the integrated circuit die 100 b are fabricated as twosegments separated by material filled in the scribe line 12therebetween. The segmented conductive line arrangement provides moredesign flexibility. For example, neighboring integrated circuit dies mayhave edge interconnect features at different layers, at differentplacements, and/or of different densities.

The continuous line features ensure that the edge interconnect features108 are exposed on the cutting surfaces 102 for subsequent wiring andpackaging process after the integrated circuit die 100 is cut free fromthe substrate 10. The symmetrical arrangement of the edge interconnectfeatures 108 also provide design flexibilities. For example, a commonscheme of edge interconnect feature arrangement may be used fordifferent integrated circuit dies, such as for different SoCs, anddifferent memory dies. It should be noted that the edge interconnectfeatures 108 may be arranged in any suitable manner to achieve desireddesign proposes.

FIGS. 1C and 1D provide additional details of the edge interconnectfeatures 108 within the integrated circuit die 100 according toembodiments of the present disclosure. FIG. 1C is an enlarged partialsectional view of the integrated circuit die 100 across the seal region.FIG. 1D is an enlarged partial sectional view of the integrated circuitdie 100 along the sealing ring 110.

As shown in FIGS. 1C and 1D, the device layer 120 is formed in and/or onthe substrate 10, and the interconnect structure 122 are formed over thedevice layer 120. The device layer 120 may include various semiconductordevices, such as transistors, diodes, capacitors, resistors, etc., andmay be formed in and/or on the substrate 10. In some embodiments, thedevice layer 120 includes one or more dielectric layers overlying thesemiconductor devices therein.

The interconnection structure 122 includes various conductive features,such as a first plurality of conductive features 126 and secondplurality of conductive features 128, and one or more intermetaldielectric (IMD) layers 124 to separate and isolate various neighboringconductive features 126, 128. In some embodiments, the first pluralityof conductive features 126 are conductive vias and the second pluralityof conductive features 128 are conductive lines. The interconnectionstructure 122 includes multiple levels of the conductive features 128,and the conductive features 128 are arranged in each level to provideelectrical paths to the devices in the device layer 120. The conductivefeatures 126 provide vertical electrical routing from the device layer120 to the conductive features 128, and between the conductive features128 in different layers.

The conductive features 126 and conductive features 128 may be made fromone or more electrically conductive materials, such as one or morelayers of graphene, metal, metal alloy, metal nitride, or silicide. Forexample, the conductive features 126 and the conductive features 128 aremade from copper, aluminum, aluminum copper alloy, titanium, titaniumnitride, tantalum, tantalum nitride, titanium silicon nitride,zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride,tungsten silicon nitride, platinum, chromium, molybdenum, hafnium, othersuitable conductive material, or a combination thereof.

The IMD layers 124 may be formed, for example, of a low dielectricconstant (low-K) dielectric material, such as SiOx, SiOxCyHz, SiOxCy,SiCx, SiNx, or related low-k dielectric material, compounds thereof,composites thereof, combinations thereof, or the like. The IMD layers124 may be formed by any suitable method, such as spinning, chemicalvapor deposition (CVD), and/or plasma-enhanced CVD (PECVD). In someembodiments, the interconnect structure 122 may be formed sequentiallylayer-by-layer from the device layer 120 during BOEL processing. In someembodiments, the interconnect structure 122, the conductive features 126and conductive features 128 may be fabricated using damascene and/ordual-damascene process.

As shown in FIG. 1C, a plurality of IMD layers 124 are sequentiallyformed over the device layer 120 with the conductive features 126, 128having increased dimension. The number of IMD layers 124 may be anynumber suitable for the circuit design. For example, the number of IMDlayers 124 may be between 1 and 30. In FIG. 1C, the IMD layers 124 aredivided into three groups: bottom IMD layers 124 x, middle IMD layers124 y, top IMD layers 124 z based on relative position to the devicelayer 120. The bottom IMD layers 124 x, formed immediately on the devicelayer 120 are thinner and with the conductive features 126, 128 of ahigher density. The middle IMD layers 124 y formed over the bottom IMDlayers 124 x are thicker and with the conductive features 126, 128 of alower density. The top IMD layers 124 z formed over the middle IMDlayers 124 y are thickest and with the conductive features 126, 128 of alowest density.

The sealing rings 110, 112 are formed in the seal region 106 between thecircuit region 104 and the scribe line 12. Each of the sealing rings110, 112 includes physically connected components to function as abarrier between the conductive features 126, 128 in the interconnectstructure 122 and exterior environment, such as moisture. The sealingrings 110, 112 may be formed by any suitable designs and with anysuitable materials, such as materials suitable as moisture barrier. Insome embodiments, the sealing rings 110, 112 are formed withelectrically conductive materials. In some embodiments, the sealingrings 110, 112 may be electrically grounded. In some embodiments, thesealing rings 110, 112 may be formed from the same material as theconductive features 126, 128. For example, the sealing rings 110, 112may be formed from Cu, Al, Co, Ru, Mo, W, and related alloys.

FIGS. 1C and 1D schematically demonstrate one example of the sealingrings 110, 112. Other sealing ring structures may be used by personsskilled in the art with the integrated circuit die 100 according topresent disclosure. As shown in FIGS. 1C and 1D, each of the sealingrings 110, 112 includes layers of substantially continuous sealing lines1101, 1121 connected by a plurality of sealing vias 110 v, 112 v formedin the IMD layers 124. The continuous sealing lines 1101, 1121 inneighboring IMD layers 124 are connected by the plurality of sealingvias 110 v, 112 v respectively. The sealing lines 1101, 1121 and sealingvias 110 v, 112 v may be fabricated layer-by-layer in the same processwith the conductive features 126, 128 in the corresponding IMD layers124. Dimension of the sealing lines 1101, 1121 may vary in different IMDlayers 124. In some embodiments, the sealing lines 1101, 1121 may have aline width 106 w in a range between about 0.01 μm and about 6 μm, and aline depth 106 d in a range between about 0.01 μm and about 6 μm.

The edge interconnect features 108 may be formed in one or more IMDlayers 124. Each of the edge interconnect features 108 may be conductiveline having an inner end 108 i and an outer end 1080. The inner end 108i may be electrically connected to one or more conductive features 128,126 in the circuit region 104. The outer end 108 o is embedded in thescribe line 12 outside the seal region 106. In some embodiments, aportion of the edge interconnect features 108 may be dummy connectors toachieve structural uniformity in the integrated circuit die 100. Forexample, the inner end 108 i of a portion of the edge interconnectfeatures 108 may be “floating” in the IMD layer 124 without connectingto any other conductive features, such as conductive features 126, 128.After the integrated circuit die 100 is cut out, the outer ends 108 o ofthe edge interconnect features 108 is exposed on the cutting surface102.

The edge interconnect features 108 extend through the sealing rings 110,112 through openings 130 which are formed in the sealing ring 110, 112and the corresponding IMD layer 124. Dielectric material of the IMDlayer 124 is disposed between the edge interconnect features 108 and thesealing rings 110, 112 to electrically isolate the edge interconnectfeatures 108 from the sealing rings 110, 112.

The edge interconnect features 108 may be formed in the same processwith the conductive features 126, 128 in the corresponding IMD layers124. In some embodiments, the sealing rings 110, 112 may be formed fromthe same material as the conductive features 126, 128. For example, theedge interconnect features 108 may be formed from Cu, Al, Co, Ru, Mo, W,and related alloys.

In some embodiments, dimensions of the edge interconnect features 108may be similar to the conductive features 128 in the same IMD layer 124.In some embodiments, the edge interconnect features 108 may have a linewidth 108 w in a range between about 0.01 μm and about 6 μm, and a linedepth 108 d in a range between about 0.01 μm and about 6 μm. A width 130w of the openings 130 may be in a range between about 0.03 μm and about18 μm.

Dimension of the edge interconnect features 108 may vary in differentIMD layers 124. Depending on the function and density of the edgeinterconnect features 108, the edge interconnect features 108 may beformed in the bottom IMD layers 124 x, the middle IMD layers 124 y, thetop IMD layers 124 z, and a top metal layer (not shown) above the topIMD layer 124 z. For example, if the edge interconnect features 108 areused to transfer signals to individual devices in the device layer 120,the density of the edge interconnect features 108 is likely to berelatively high and the width of the edge interconnect features 108 maybe relatively small, and the edge interconnect features 108 may beformed in one or more bottom IMD layers 124 x. If the edge interconnectfeatures 108 are used to provide power supply to the device layer 120,the density of the edge interconnect features 108 is likely to berelatively low and the width of the edge interconnect features 108 maybe relatively large, and the edge interconnect features 108 may beformed in one or more top IMD layers 124 z.

In some embodiments, the scribe lines 12 between the integrated circuitdies 100 may also be filled with suitable materials. A dielectricmaterial may be filled in the scribe lines 12 between the integratedcircuit dies 100. The outer end 1080 of the edge interconnect features108 are surrounded by the dielectric material in the scribe lines 12,thus, are electrically isolated from one another. In some embodiments,the scribe lines 12 may be filled with the same material as in the IMDlayers 124. The scribe lines 12 may be filled and then patternedlayer-by-layer in the same process with the conductive features 126, 128in the corresponding IMD layers 124. In some embodiments, the scribelines 12 or the dielectric material filled in the scribe lines 12 mayinclude one or more layers of a low dielectric constant (low-K)dielectric material, such as SiOx, SiOxCyHz, SiOxCy, SiCx, SiNx, orrelated low-k dielectric material, compounds thereof, compositesthereof, combinations thereof, or the like.

In the embodiment shown in FIGS. 1C and 1D, the edge interconnectfeatures 108 are formed in the top IMD layer 124 z. As discussed above,the edge interconnect features 108 according to the present disclosuremay be formed in any suitable IMD layers. In the embodiment shown inFIGS. 1E and 1F, the edge interconnect features 108 are formed in themiddle IMD layer 124 y. In the embodiment shown in FIGS. 1G and 1H, theedge interconnect features 108 are formed in the bottom IMD layer 124 x.

In the embodiment shown in FIGS. 11 and 1J, the edge interconnectfeatures 108 are formed in two or more IMD layers 124. Particularly, inFIGS. 11 and 1J, the edge interconnect features 108 are formed in one ofthe bottom IMD layer 124 x and in one of the top IMD layer 124 z. Itshould be noted that the edge interconnect features 108 may be formed inany combination of IMD layers 124.

In some embodiments, the edge interconnect features 108 may be formed ina top metal layer, which may be the topmost layer of the IMD layer 124or a metal layer immediately under an under-bump metallization (UBM)structure. In the embodiment shown in FIGS. 1L and 1K, the edgeinterconnect features 108 are formed in the top metal layer.

As shown in FIG. 1L, a dielectric layer 132 is formed over the topmostIMD layer 124. One or more contact pads 134 are formed on theinterconnect structure 122 to electrically connect the metal lines orvias inside the IMD layers 124. In some embodiments, the contact pads134 may be formed of aluminum, aluminum copper, aluminum alloys, copper,copper alloys, or the like. A passivation layers, such as a firstpassivation layer 136 and a second passivation layer 138 are formed overthe dielectric layer 132 and patterned to expose portions of the contactpads 134 respectively. In some embodiments, the first passivation layer136 is formed of a dielectric material, such as undoped silicate glass(USG), silicon nitride, silicon oxide, silicon oxynitride or anon-porous material by any suitable method, such as CVD, PVD, or thelike. The second passivation layer 138 may be a polymer layer, such asan epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), orthe like, although other relatively soft, often organic, dielectricmaterials can also be used. Bumps 140 are formed on the correspondingcontact pads 134. The bump 140 can be a spherical bump or a pillar bumpformed of a conductive material including at least one of solder, Cu, Nior Au.

As shown in FIGS. 1L and 1K, the edge interconnect features 108 may beformed in the top metal layer and to provide connection to the devicesin the device layer 120 in electrical communication with the bumps 140.

FIGS. 2, 3A-3D, 4A-4D, 5A-5B, 6, and 7 schematically demonstrate variousstages of forming a semiconductor package 300 according to embodimentsof the present disclosure. The semiconductor package 300 includes two ormore integrated circuit dies having edge interconnect features accordingto the present disclosure.

FIG. 2 is schematic plan views of substrates 10 a, 10 b, 10 c havingintegrated circuit dies 200 a, 200 b, 200 c formed thereon. FIG. 3A is aschematic plan view of the semiconductor package 300. FIG. 3B is aschematic cross-sectional view of the semiconductor package 300. FIG. 3Cis a partial enlarged view of the area 3C in FIG. 3A. FIG. 3D is apartial enlarged view of the area 3D in FIG. 3B.

As shown in FIG. 2 , the integrated circuit dies 200 a, 200 b, 200 c maybe fabricated separately on different substrates 10 a, 10 b, 10 c.Alternatively, some or all of the integrated circuit dies 200 a, 200 b,200 c may be fabricated on the same substrate.

In some embodiments, the integrated circuit dies 200 a, 200 b, 200 c mayinclude any suitable circuit designs to achieve different functions. Forexample, each of the integrated circuit dies 200 a, 200 b, 200 c may bea system on a chip (SOC) or a system on integrated circuit (SOIC) die; amemory die, such as a static random-access memory (SRAM) die, a dynamicrandom-access memory (DRAM) die, a high bandwidth memory (HBM) die, orthe like; a passive device die, such as a multilayer ceramic chip (MLCC)capacitor die, an integrated passive device (IPD) die, an integratedvoltage regulator (IVR) die, the like, or a combination thereof; a logicdie; an analog die; a microelectromechanical system (MEMS) die, a radiofrequency (RF) die, or a combination thereof.

In some embodiments, the integrated circuit dies 200 a, 200 b, 200 c maybe different types of dies to be connected together. For example, theintegrated circuit die 200 a may be a SOC die and the integrated circuitdies 200 b and 200 c may be memory dies, such as a HBM die and a DRAMdie.

Similar to the integrated circuit die 100 described in FIGS. 1A-1K, eachof the integrated circuit dies 200 a, 200 b, 200 c may include a devicelayer 220 a, 220 b, 220 c formed in and/or on the substrate 10 a, 10 b,10 c, and an interconnect structure 222 a, 220 b, 220 c formed on thedevice layer 220 a, 220 b, 220 c (shown in FIG. 3B). The interconnectstructures 222 a, 222 b, 222 c are similar to the interconnect structure122 of the integrated circuit die 100. Similar to the integrated circuitdie 100, each of the integrated circuit die 200 a, 200 b, 200 c furtherincludes one or more edge interconnect features 208 a, 208 b, 208 cextending from the interconnect structures 222 a, 222 b, 222 c intoscribe lines 12 a, 12 b, 12 c on the corresponding substrate 10 a, 10 b,10 c. After the integrated circuit dies 200 a, 200 b, 200 c arefabricated and cut into individual dies, the edge interconnect features208 a, 208 b, 208 c are exposed on corresponding cutting surfaces 202 a,202 b, 202 c. As shown in FIGS. 3C and 3D, cross-sectional surfaces 208s of the edge interconnect features 208 a, 208 c are exposed on thecutting surfaces 202 a, 202 c.

In some embodiments, the edge interconnect features 208 a, 208 b, 208 cin the integrated circuit dies 200 a, 200 b, 200 c are arranged in thesame pattern, i.e. arranged in substantially the same intervals so thatthe edge interconnect features 208 a, 208 b, 208 c may be connected withone another in the subsequent packaging processes.

As shown in FIGS. 3A and 3B, the integrated circuit dies 200 a, 200 b,200 c are attached to a carrier substrate 302. In some embodiments, anadhesive layer 304 is formed on the carrier substrate 302, and a dieattach film 306 is formed on the adhesive layer 304. The integratedcircuit dies 200 a, 200 b, 200 c are attached on the die attach film306. The carrier substrate 302 may be a glass carrier substrate, aceramic carrier substrate, or the like. In some embodiments, multiplesemiconductor packages can be formed on the carrier substrate 302simultaneously.

The adhesive layer 304 is placed on the carrier substrate 302 to assistin the adherence of overlying structures, for example, the integratedcircuit dies 200 a, 200 b, 200 c. In some embodiments, the adhesivelayer 304 may comprise a light to heat conversion (LTHC) material or anultra-violet glue, although other types of adhesives, such as pressuresensitive adhesives, radiation curable adhesives, epoxies, combinationsof these, or the like, may also be used. The adhesive layer 304 may beplaced onto the carrier substrate 302 in a semi-liquid or gel form,which is readily deformable under pressure. In other embodiments, theadhesive layer 304 may be an ultra-violet (UV) glue, which loses itsadhesive property when exposed to UV lights.

The die attach film 306 may be placed on the adhesive layer 304 toassist in the attachment of the integrated circuit dies 200 a, 200 b,200 c to the adhesive layer 304. In some embodiments, the first dieattach film 306 may be an epoxy resin, a phenol resin, acrylic rubber,silica filler, or a combination thereof, and is applied using alamination technique. The die attach film 306 may be dispensed as aliquid and cured, may be a laminate film laminated onto the carriersubstrate 302, or may be the like. In some embodiments, the top surfaceof the die attach film 306 may be leveled and may have a high degree ofcoplanarity. However, any other suitable alternative material and methodof formation may alternatively be utilized.

As shown in FIGS. 3B, the integrated circuit dies 200 a, 200 b, 200 care placed onto the die attach film 306. The integrated circuit dies 200a, 200 b, 200 c may be placed using, e.g., a pick and place process, ina face-up orientation. However, any suitable method of placing theintegrated circuit dies 200 a, 200 b, 200 c onto the die attach film 306may also be utilized.

In some embodiments, the integrated circuit dies 200 a, 200 b, 200 c maybe placed onto the carrier substrate 302 so that the edge interconnectfeatures 208 a, 208 b, 208 c are aligned to allow inter-chip connectors310 (FIG. 4A) to be formed therebetween. As shown in FIG. 3A, theintegrated circuit dies 200 a, 200 b, 200 c may be placed so that one ofthe cutting surfaces 202 a, 202 b, 202 c in each of the integratedcircuit dies 200 a, 200 b, 200 c faces one of the cutting surfaces 202a, 202 b, 202 c of the integrated circuit dies 200 a, 200 b to beconnected. In FIG. 3A, the integrated circuit dies 200 b, 200 a, 200 care positioned in a linear arrangement so that the edge interconnectfeatures 208 a of the integrated circuit die 200 a are to be connectedwith the edge interconnect features 208 b of the integrated circuit die200 b and the edge interconnect features 208 c of the integrated circuitdie 200 c.

The integrated circuit dies 200 a, 200 b, 200 c are placed on thecarrier substrate 302 with a gap 308 between the cutting surfaces 202 a,202 b, 202 c of the integrated circuit dies 200 a, 200 b, 200 c to beconnected. The gap 308 may have a distance 308 w between the cuttingsurfaces 202 a, 202 b, 202 c. In some embodiments, the distance 308 wmay be in arrange between about 1 μm and about 200 μm. A distance lessthan 1 μm may not be wide enough to properly fill an encapsulant layertherebetween. A distance greater than 200 μm may be too wide to formindividual inter-chip connectors therebetween.

FIG. 3C schematically illustrates the alignment between the edgeinterconnect features 208 a of the integrated circuit die 200 a and theedge interconnect features 208 c of the integrated circuit die 200 c inthe x-y plane. As shown in FIG. 3C, the edge interconnect features 208a, 208 b, 208 c of the integrated circuit die 200 a, 200 b, 200 c mayhave substantially the same spacing as in the integrated circuit die 200a, 200 b, 200 c to be connected. FIG. 3D schematically illustrates thealignment between the edge interconnect features 208 a of the integratedcircuit die 200 a and the edge interconnect features 208 c of theintegrated circuit die 200 c in the z-direction. As shown in FIG. 3D,the edge interconnect features 208 a, 208 c may be formed in the IMDlayer at the substantially the same distance from a bottom of thecorresponding integrated circuit die 200 a, 200 c.

Referring FIG. 3B, an optional dielectric layer (not shown) may beformed between the die attach film 306 and the integrated circuit dies200 a, 200 b, 200 c on the backside of the integrated circuit dies 200a, 200 b, 200 c. One or more metallization patterns are formed on or inthe dielectric layer to form a redistribution structure, such as powerrails formed on a backside of the substrate 10 a, 10 b, 10 c.

After the integrated circuit dies 200 a, 200 b, 200 c are attached tothe carrier substrate 302, a bumping process is performed to forminter-chip connectors 310 between the edge interconnect features 208 a,208 b, 208 c, as shown in FIGS. 4A-4D. FIG. 4A schematic cross-sectionalview of the semiconductor package 300. FIG. 4B is a partial enlargedview of the area 4B in FIG. 4A. FIGS. 4C and 4D are partial enlargedviews of the area 3C in FIG. 3A.

The inter-chip connectors 310 may be formed by a selective bumpingprocess. In some embodiments, the exposed cross-sectional surfaces 208 sact as catalyst or a seed layer for a selective deposition process. Theinter-chip connectors 310 may be formed by any suitable depositionprocess, for example, by electroless deposition or by an atomic layerdeposition (ALD) or by chemical vapor deposition (CVD). As shown in FIG.4C, conductive bumping features 310 a, 310 b (shown in FIG. 4A), 310 cmay selectively form on the exposed cross-sectional surfaces 208 s ofthe edge interconnect features 208 a, 208 b, 208 c. As the selectivedeposition continues, the conductive bumping features 310 a, 310 b, 310c increase in dimension and join with the conductive bumping features310 a, 310 b, 310 c grown from the exposed cross-sectional surfaces 208s on the opposite side of the gap 308, and forming the inter-chipconnectors 310, as shown in FIG. 4D. The conductive bumping features 310a, 310 b, 310 c on the cutting surfaces 202 a, 202 b, 202 c withoutfacing other integrated circuit dies may remain hanging, as shown inFIG. 4A.

After opposing conductive bumping features 310 a, 310 b, 310 c areconnected with each other, the selective deposition process may beperformed for an additional time period to increase cross sectionalareas of the inter-chip connectors 310, thus, reducing resistance of theinter-chip connectors 310.

In some embodiments shown in FIG. 5B, each of the inter-chip connectors310 may be conductive columns having a first end 3101 and a second end3102. The first end 3101 is in contact with the exposed surface 208 s ofthe edge interconnect feature 208 in a first integrated circuit die,such as the integrated circuit die 208 a. The second end 3102 is incontact with the exposed surface 208 s of the edge interconnect feature208 in a second integrated circuit die, such as the integrated circuitdie 202 c. In some embodiments, a portion of the first end 3101 andsecond end 3102 may also be in contact with the cutting surface 202 ofthe integrated circuit dies 200 a, 200 c.

The inter-chip connectors 310 may have an average diameter 310D. In someembodiments, the average diameter 310D of the inter-chip connectors 310may be in a range between 0.02 μm and about 12 μm. An average diameterless than 0.01 μm may not provide enough reliable electrical connectionbetween the edge interconnect features 208 a, 208 b, 208 c. An averagediameter greater than 12 μm may cause short circuit between neighboringinter-chip connectors 310. In some embodiments, when the inter-chipconnectors 310 are formed by electroless plating, the thickness of theinter-chip connectors 310 may be non-ununiformed. For example, theinter-chip connectors 310 formed by plating will be formed inX-direction and simultaneously in Z-direction, thus, the portion closerto the edge interconnect features 208 a/208 c will be thicker than theportions further away from the edge interconnect features 208 a/208 c.

The inter-chip connectors 310 and the conductive bumping features 310 a,310 b, 310 c may be formed from any suitable conductive material. Insome embodiments, the inter-chip connectors 310 and the conductivebumping features 310 a, 310 b, 310 c may be formed from a metal, such asCu, Co, Ru, Mo, W, Ir, Fe, Ni, Sn, Ag, alloys thereof, or a combinationthereof.

In some embodiments, the inter-chip connectors 310 and the conductivebumping features 310 a, 310 b, 310 c may be formed by an electrolessdeposition process. The electroless deposition may be performed in aplating solution having a pH value in a range between about 2.0 andabout 11.0. The electroplating deposition may be performed in atemperature range between room temperature and about 180° C. Theelectroless deposition solution may comprise reactant includingmetal-organic and metal-halide structures, such as Metal-CxHyOz,Metal-CxNyHz, Metal-CxOy, Metal-NxHy, Metal-Fx, Metal-Clx, Metal-Brx,the like, and a combination thereof. The metal may include Cu, Co, Ru,Mo, W, Ir, Fe, Ni, Sn, Ag, alloys thereof, or a combination thereof. Theelectroless deposition solution may be a water-based solution or asolvent-based solution. When a solvent-based solution is used, theprocess temperature may be performed between room temperature to about180° C.

In other embodiments, the inter-chip connectors 310 and the conductivebumping features 310 a, 310 b, 310 c may be formed by selective ALD/CVDprocess, for example by plasma enhanced ALD, plasma enhanced CVD,thermal ALD, or thermal CVD. Particularly, selective ALD/CVD may beachieved through surface reaction, surface state such as H-terminationand surface free electron, and the sacrificial solid-state co-reactant.In some embodiments, selective deposition is enabled by catalyticbehavior of a metal surface which promotes precursor reduction. TheALD/CVD process may be performed at a pressure range between about 500mtorr and about 1 atm. The ALD/CVD may be performed in a temperaturerange between room temperature and about 550° C. The ALD/CVD processprecursors may include metal-organic and metal-halide structures, suchas Metal-CxHyOz, Metal-CxNyHz, Metal-CxOy, Metal-NxHy, Metal-Fx,Metal-Clx, Metal-Brx, the like, and a combination thereof. The metal mayinclude Cu, Co, Ru, Mo, W, Ir, Fe, Ni, Sn, Ag, alloys thereof, or acombination thereof. In some embodiments, selective ALD may be performedby forming a catalytic contribution of surface free electrons on exposedmetal surface and then selective reaction between the terminatedhydrogen and the methyl radical of metal-halide structure. In anotherembodiment, selective CVD is performed to form cobalt on exposed edgeinterconnect features 208 from dicobaltoctacarbonyl andtrimethylphosphine.

The inter-chip connectors 310 connect the devices in two integratedcircuit dies 208 a, 208 b, 208 c without going through any interposer(e.g., interposer substrate 316 in FIG. 6 ) or external connectors(e.g., external contacts 314 in FIG. 6 ), thus, lower power consumption.The inter-chip connectors 310 and the edge interconnect features 208 a,208 b, 208 c are formed in the IMD layer level, thus, with higherrouting density than bumping connectors formed on or aboveredistribution layer.

After formation of the inter-chip connectors 310, an encapsulant layer312 is formed over various components, including the inter-chipconnectors 310, on the carrier substrate 302, as shown in FIGS. 5A and5B. FIG. 5A is a schematic cross-sectional view of the semiconductorpackage 300. FIG. 5B is a partial enlarged view of the area 5B in FIG.5A.

The encapsulant layer 312 may be a molding compound, epoxy, or the like,and may be applied by compression molding, lamination, transfer molding,or the like. The encapsulant layer 312 may be formed over the carriersubstrate 302 such that the inter-chip connectors 310 and the conductivebumping features 310 a, 310 b, 310 c hanging on the cutting surface 202s are buried or covered. The encapsulant layer 312 may then be cured.

In some embodiments, the encapsulant layer 312 may undergo a grindingprocess to expose conductive features on the integrated circuit dies 200a, 200 b, 200 c so that external connectors may be formed. FIG. 6schematic cross-sectional view of the semiconductor package 300 showingsubsequent process after forming the encapsulant layer 312. Externalcontacts 314 may be formed on the integrated circuit dies 200 a, 200 b,200 c, for example, by a bumping process. The external contacts 314 maybe, e.g., conductive pillars such as a copper pillars or copper posts.In some embodiments, the external contacts 314 may be solder bumps,copper bumps, or other suitable external contacts that may be made toprovide electrical connection from the integrated circuit dies 200 a,200 b, 200 c to other external devices. All such external contacts arefully intended to be included within the scope of the embodiments. Asthe inter-chip connectors 310 provide internal connections between oramong the integrated circuit dies 200 a, 200 b, 200 c, the externalcontacts 314 may be used to provide external connections to theintegrated circuit dies 200 a, 200 b, 200 c.

In some embodiments, an optional interposer substrate 316 may beattached to the external contacts 314. The interposer substrate 316 mayinclude various embedded interconnections, which may provide routes fromthe external contacts 314 to external circuits, such as a printedcircuit board.

An encapsulant layer 318 may then be formed over the interposersubstrate 316. The encapsulant layer 318 may be a molding compound,epoxy, or the like, and may be applied by compression molding,lamination, transfer molding, or the like. The encapsulant layer 318 maybe formed over the interposer substrate 316 such that the externalcontacts 314 are buried or covered. The encapsulant layer 318 may thenbe cured. In some embodiments, the encapsulant layer 318 and theencapsulant layer 312 may be formed from the same material.

In some embodiments, the encapsulant layer 318 may undergo a grindingprocess to expose conductive features on the interposer substrate 316.External connectors 320 are then formed on the interposer substrate 316.The external connectors 320 may be used to connect the semiconductorpackage 300 to a printed wiring board or printed circuit board (PCB) toform an electronic assembly. In some embodiments, through substrate viasor TSVs 317 extend vertically through the interposer substrate 316 andelectrically connect the external connectors 320 and the externalcontacts 314. In some embodiments, the TSVs 317 may be through siliconvias where a silicon substrate material is used. TSVs 317 may be made ofany suitable conductive material commonly used in the art for such vias,including without limitation tungsten, copper, nickel, or alloysthereof. In some representative embodiments, TSVs 317 may have arepresentative diameter, without limitation, of about 5 microns to about12 microns depending on the design requirement and process used to formthe TSVs 317.

FIG. 7 schematic cross-sectional view of the semiconductor package 300attached to a PCB 322, with the carrier substrate 302 along with theadhesive layer 304 and the die attach film 306 removed. The PCB 322 maybe part of an electronic assembly can be part of an electronic systemsuch as computers, wireless communication devices, computer-relatedperipherals, entertainment devices, or the like.

Even though three integrated circuit dies 200 a, 200 b, 200 c are shownin the semiconductor package 300, less or more integrated circuit dieswith edge interconnect features may be packaged together according tocircuit design.

Even though the integrated circuit dies 200 a, 200 b, 200 c in thesemiconductor package 300 have substantially the same shape and thedimension, integrated circuit dies of different dimension and/or shapemay be included in the semiconductor packages so along as edgeinterconnect features in different integrated circuit dies to beconnected may be aligned for connection.

Embodiments of the present disclosure provide an integrated circuit diewith edge interconnect features extending from one or more IMD layers toa side surface of the integrated circuit die. The edge interconnectfeatures of different integrated circuit dies may be connected by aselective bumping process to enable direct connection between theintegrated circuit dies. The direct connection between differentintegrated circuit dies reduces interposer layers, redistributionprocess, and bumping processes in multi-die integration, thus, reducingcost of manufacturing. The edge interconnect features also enable powerto be directly transferred therethrough, instead of going throughinterposer substrates, or PCBs, thus achieve higher performance. Theedge interconnect features, connected to one or more IMD layers, alsoenables higher routing density than through an interposer. The edgeinterconnect features design may be easily adopted from one integratedcircuit die to another, thus, provide high feasibility and flexibilityfor designers.

Some embodiments of the present provide a semiconductor packagecomprising a first integrated circuit die having a first cuttingsurface, wherein the first integrated circuit die comprises a first edgeinterconnect feature extending to the first cutting surface, a secondintegrated circuit die having a second cutting surface, wherein thesecond integrated circuit die comprises a second edge interconnectfeature extending to the second cutting surface, and an inter-chipconnector having a first end contacting the first edge interconnectfeature and a second end contacting the second edge interconnectfeature.

Some embodiments of the present disclosure provide a semiconductorpackage. The semiconductor package includes a substrate, a firstintegrated circuit die attached to the substrate, wherein the firstintegrated circuit die has a first cutting surface, a second integratedcircuit die attached to the substrate adjacent the first integratedcircuit die, wherein the second integrated circuit die has a secondcutting surface, and the first cutting surface faces the second cuttingsurface, and a plurality of inter-chip connectors formed between thefirst integrated circuit die and second integrated circuit die, whereina first end of each of the inter-chip connector contacts the firstcutting surface and a second end of the inter-chip connector contactsthe second cutting surface.

Some embodiments of the present disclosure provide a method for forminga semiconductor device. The method includes forming a first integratedcircuit die having a first edge interconnect feature, and a secondintegrated circuit die having a second edge interconnect feature,wherein the first edge interconnect feature is exposed on a cuttingsurface of the first integrated circuit die, and the second edgeinterconnect feature is exposed on a cutting surface of the secondintegrated circuit die, positioning the first and second integratedcircuit dies adjacent to each other such that the first edge conductivefeature faces the second edge conductive feature, and forming aninter-chip connector between the first edge conductive feature and thesecond edge conductive feature.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

1. A semiconductor package, comprising: a first integrated circuit diehaving a first cutting surface, wherein the first integrated circuit diecomprises a first edge interconnect feature extending to the firstcutting surface; a second integrated circuit die having a second cuttingsurface, wherein the second integrated circuit die comprises a secondedge interconnect feature extending to the second cutting surface; andan inter-chip connector having a first end contacting the first edgeinterconnect feature and a second end contacting the second edgeinterconnect feature.
 2. The semiconductor package of claim 1, whereinthe first integrated circuit die further comprises a first interconnectstructure, and the first edge interconnect feature is connected to thefirst interconnect structure.
 3. The semiconductor package of claim 2,wherein the first interconnect structure comprises: an IMD (inter metaldielectric) layer; and a conductive feature embedded in the IMD layer,wherein an inner end of the first edge interconnect feature is connectedto the conductive feature, and an outer end of the first edgeinterconnect feature extends to the first cutting surface of the firstinterconnect feature.
 4. The semiconductor package of claim 3, whereinthe first interconnect structure further comprises a sealing ring, andthe first edge interconnect feature extends through an opening in thesealing ring.
 5. The semiconductor package of claim 4, furthercomprising an encapsulant layer formed between the first integratedcircuit die and the second integrated circuit die, and wherein theinter-chip connector is formed in the encapsulant layer.
 6. Thesemiconductor package of claim 3, wherein the first integrated circuitdie further comprises a plurality of external contacts formed on thefirst interconnect structure.
 7. The semiconductor package of claim 6,further comprising an interposer substrate attached to the plurality ofexternal contacts of the first integrated circuit die.
 8. Asemiconductor package, comprising: a substrate; a first integratedcircuit die attached to the substrate, wherein the first integratedcircuit die has a first cutting surface; a second integrated circuit dieattached to the substrate adjacent the first integrated circuit die,wherein the second integrated circuit die has a second cutting surface,and the first cutting surface faces the second cutting surface; and aplurality of inter-chip connectors formed between the first integratedcircuit die and second integrated circuit die, wherein a first end ofeach of the inter-chip connector contacts the first cutting surface anda second end of the inter-chip connector contacts the second cuttingsurface.
 9. The semiconductor package of claim 8, wherein the substrateis an interposer substrate, and the first integrated circuit dieconnected to the interposer substrate through a plurality of firstexternal contacts.
 10. The semiconductor package of claim 9, furthercomprising an encapsulant layer, wherein the plurality of inter-chipconnectors are embedded in the encapsulant layer.
 11. The semiconductorpackage of claim 8, wherein the first integrated circuit die comprises:one or more transistors; an interconnect structure comprising two ormore IMD layers formed over the one or more transistors; and a pluralityof edge interconnect features, wherein each of the plurality of edgeinterconnect feature has an inner end embedded in one of the two or moreIMD layers and an outer end in contact with one of the plurality of theinter-chip connectors.
 12. The semiconductor package of claim 11,wherein the interconnect structure comprises a sealing ring formed inthe two or more IMD layers, and the plurality of edge interconnectfeatures extend through openings in the sealing ring.
 13. Thesemiconductor package of claim 11, wherein the first integrated circuitdie has four cutting surfaces including the first cutting surface, andthe plurality of edge interconnect features are symmetricallydistributed along all of the four cutting surfaces of the firstintegrated circuit die.
 14. The semiconductor package of claim 13,further comprises a plurality of conductive bumping features in contactwith the plurality of edge interconnect features on all of the fourcutting surfaces of the first integrated circuit die.
 15. Asemiconductor package, comprising: a first integrated circuit die havinga first edge interconnect feature; a second integrated circuit diehaving a second edge interconnect feature, wherein the first and secondintegrated circuit dies are positioned adjacent to each other such thatthe first edge conductive feature faces the second edge conductivefeature; and an inter-chip connector formed between the first edgeconductive feature and the second edge conductive feature.
 16. Thesemiconductor package of claim 15, further comprising an encapsulantlayer formed between the first integrated circuit die and the secondintegrated circuit die, and the inter-chip connector is embedded in theencapsulant layer.
 17. The semiconductor package of claim 16, whereinthe inter-chip connector is formed by an electroless deposition processprior to deposition of the encapsulate layer.
 18. The semiconductorpackage of claim 15, further comprising an interposer substrate attachedto the plurality of external contacts of the first integrated circuitdie.
 19. The semiconductor package of claim 15, wherein the firstintegrated circuit die comprises: a device layer including one or moresemiconductor devices; and an IMD layer formed over the device layer,wherein the first edge interconnect feature is formed in the IMD layer.20. The semiconductor package of claim 19, where the first integratedcircuit die further comprises a sealing ring in the IMD layer adjacent aperimeter of the first integrated circuit die, the sealing ring has anopening, and the first edge interconnect feature extends through theopening.